This invention relates generally to an electrostatic discharge protection circuit, and more specifically to an electrostatic discharge protection circuit utilizing a saturation resistor.
One problem facing the designers of metal oxide semiconductor (MOS) integrated circuits or complementary metal oxide semiconductor (CMOS) integrated circuits is the problem of protecting the gate insulator used in those circuits from electrostatic discharge (ESD). This problem becomes especially acute in CMOS circuits that use a very thin gate insulator. Currently circuits referred to as deep submicron CMOS integrated circuits are expected to have gate insulators as thin as 2 nanometers (nm). Breakdown voltages for such thin insulators, usually oxides, can be on the order of a few volts for ESD transients. ESD transients are typically low energy, high current pulses that can be modeled as a current source with a current having a magnitude on the order of amperes. The problem of protecting the thin insulator of the integrated circuit becomes one of shunting the ESD transient current so that a voltage less than the destructive breakdown voltage is applied across any gate insulator.
The input signals applied to an MOS circuit are applied to an input terminal. An input only terminal of an MOS circuit has MOS transistor gates electrically coupled to the terminal. An ESD transient appearing on the input terminal is thus applied directly across the gate insulator of the input MOS transistor or from the gate of the MOS transistor to the drain, source, and/or body of the transistor. Hence the need to protect the gate insulator of transistors exposed to an ESD transient appearing at an input terminal is widely recognized and, accordingly, a great deal of effort has been spent trying to protect the gate insulator of those input transistors from the damaging effects of ESD transients. One solution that has been applied for protecting the transistors at the circuit input is to use an attenuation network including four diodes and a series resistor. During an ESD transient, two diodes positioned at the input terminal are used as the primary transient current shunt path. The series resistor and the additional two diodes, connected across the input transistor gate, are used to provide a high impedance path for the transient such that the voltage of the transient appearing at the input terminal is attenuated before it reaches the gate of the input transistor.
The output from an MOS circuit is generally supplied by output driver transistors coupled to an output terminal. A high voltage ESD transient can also appear at the output terminal and can be applied to the gate of the driver transistors. The same attenuation networks used for ESD protection on circuit inputs, however, cannot be used for ESD transient protection of the output driver transistors. Because of the low impedance requirements of the MOS output driver transistors, the attenuation resistor would have to be of such low value that its effectiveness in attenuating an ESD transient appearing at the output terminal would be limited.
Although the output is generally taken at a drain or source of an output MOS driver transistor and not at a gate of that transistor, the ESD voltage on the output terminal appears between gate and drain or between gate and source of the output transistor. An ESD transient coupled to the output of a MOS circuit can thus be as destructive as would such a transient applied at the input of the circuit. Accordingly, a need exists for protecting the output of MOS circuits and that need is not met by the ESD protection circuits normally applied at the input of the circuit. Thus a need exists for an electrostatic discharge protection circuit for protecting the output of an MOS circuit.
In accordance with one embodiment of the invention, an electrostatic discharge protection circuit for protecting the output of an MOS circuit includes a saturation resistor coupled between the output of the circuit and the output terminal. The saturation resistor is used, in accordance with an embodiment of the invention, with an impedance device that can be coupled between the output terminal and a reference potential. The saturation resistor has the property of having a low resistance at low current values and a high resistance at high current values. Thus the saturation resistor has little effect on the output during normal operation of the device, but provides a high resistance value in series with the output transistor when an electrostatic discharge transient is applied to the output terminal of the circuit.